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論文識別碼	etd-0814107-143119
統計	本論文已被瀏覽 32 次，被下載 365 次
中文姓名	陳昀翰
英文姓名	Yun-han Chen
電子信箱	E-mail 資料不公開
系所名稱(中)	電機工程學系碩博士班
系所名稱(英)	Electrical Engineering
學年度	95
學期	2
學位	碩士
語文別	英文
論文種類	碩士論文
論文名稱(中)	應用於高速類比數位轉換器前端之五百萬赫反頻疊失真切換式電容低通濾波器
論文名稱(英)	A 5-MHz Passband Switched-Capacitor Anti-aliasing Lowpass Filter for High Speed Analog to Digital Converter Applications
頁數	80
摘要(中)	本論文提出了一個應用於高速類比數位轉換器之反頻疊失真切換式電容低通濾波器。論文中，除了使用六階的橢圓型濾波器來降低運算放大器的數量以及功率消耗之外，亦採用串接電路架構來降低對元件變化的敏感度。 我們首先使用SWITCAP來針對電路的非理想效應進行分析與模擬，運算放大器的非理想性，諸如有限低頻增益、有限頻寬及有限迴轉率等對整體濾波器效能造成影響之因素均納入考量。濾波器設計技巧，如極零點配對與排序、適應性動態範圍調整與最佳電容大小的選擇亦涵蓋在整體電路設計之中。模擬結果顯示濾波器在4.72 MHz導通頻寬內能達到0 dB增益，而導通頻帶漣波能壓抑在1.31 dB之內，且截止頻率為8 MHz，其增益為 -53 dB。此低通濾波器以0.35 μm製程設計，由佈局圖顯示晶片整體面積大約為1.8 mm × 2.1 mm。
摘要(英)	In this thesis, a switched-capacitor (SC) lowpass filter dedicated to high speed ADC applications is proposed. The six-order elliptic filter is selected to reduce the number of operational amplifiers (opamps) and power consumption. The cascade architecture is adopted which has low sensitivity to component tolerances and is efficient in its use of high-order filter circuits. The non-ideal factors within a SC filter are analyzed and modeled using SWITCAP in prior to the transistor-level design. Techniques such as zeros/poles pairing and ordering, dynamic range scaling and optimal capacitance assignment are adopted in the filter design. Simulation results show the overall filter achieves a gain of 0 dB in the passband within 4.72 MHz, with -1.31 dB of maximum passband ripple. The image rejection is under -53 dB at 8 MHz. The lowpass filter is designed with the TSMC 0.35-μm 2P4M process, and occupies an area of approximately 1.8 mm × 2.1 mm.
論文目次	Table of Contents i List of Tables iv List of Figures v Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 2 Chapter 2 Lowpass Filter Architectures 4 2.1 Classical Filter Responses 4 2.1.1 The Butterworth response 6 2.1.2 The Chebyshev response 7 2.1.3 The inverse Chebyshev response 12 2.1.4 The Cauer/Elliptic response 13 2.2 Filter Architectures 16 2.2.1 Transconductance-C 16 2.2.2 Switched-Capacitor 17 Chapter 3 Switched-Capacitor Biquadratic Filter 19 3.1 SC Resistor 20 3.2 SC Biquad 23 3.3 Switch Sharing 26 Chapter 4 Non-ideal Considerations for SC Filter 28 4.1 Lowpass SC Filter Specification 28 4.2 Zeros/Poles Pairing and Ordering 33 4.3 Dynamic Range Scaling and Optimal Capacitance Assignment 34 4.3.1 Dynamic range scaling (DRS) 36 4.3.2 Optimal capacitance assignment 37 4.4 Operational Amplifier Requirements 40 4.4.1 Finite DC gain 40 4.4.2 Finite bandwidth 43 4.4.3 Finite slew rate 48 4.5 Switch Non-idealities 49 4.6 Capacitor Mismatch Effect 51 4.7 Other Non-ideal Effects in SC Circuit Realization 53 4.7.1 Charge injection 53 4.7.2 Clock feedthrough 54 4.7.3 Cancellation of other non-ideal effects 55 Chapter 5 Implementation of a SC Filter and Simulation Results 56 5.1 Differential Operational Amplifier 56 5.1.1 Design issue of operational amplifier 57 5.1.2 Folded-cascode operational amplifier 59 5.1.4 Operational amplifier specifications 63 5.1.3 Common-mode feedback 64 5.1.5 Pre-layout simulation results of the opamp 66 5.1.6 The OTA layout and post-layout simulation results 69 5.2 SC Lowpass Filter 72 5.2.1 Pre-layout simulation result of SC lowpass filter 72 5.2.2 Layout considerations 73 Chapter 6 Conclusions and Future work 75 6.1 Conclusions 75 6.2 Future work 76 References 77
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Gregorian, K. W. Martin, and G. C. Temes, “Switched-capacitor circuit design,” Proceedings of the IEEE, vol. 71, no. 8, pp. 941-966, Aug. 1983. [9] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing. New York: Wiley, 1986. [10] Q. Huang and W. Sansen, “Design techniques for improved capacitor area efficiency in switched-capacitor biquads,” IEEE Trans. Circuits Syst., vol. 34, pp.1590-1599, Dec. 1987. [11] A. Hastings, Art of Analog Layout, Upper Saddle River, NJ: Prentice Hall, 2005. [12] E. Iroaga and B. Murmann, “A 12-Bit 75-MS/s pipelined ADC using incomplete settling,” IEEE J. Solid-State Circuits, vol. 42, pp. 748-756, Apr. 2007. [13] D. Johns, and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons, Inc. 1997. [14] W. H. Ki and G. C. Temes, “Area-efficient gain- and offset-compensated very large time-constant biquads,” in Proc. IEEE ISCAS, May 1992, pp. 1187-1190. [15] W. H. Ki and G. C. Temes, “Optimal capacitance assignment of switched-capacitor biquads,” IEEE Trans. Circuits Syst. I, vol. 42, pp. 334-342, June 1995. [16] K. B. H. Khoo, “Programmable high-dynamic range sigma-delta A/O converters for multistandard fully-integrated RF receivers (CMOS),” EECS Department, University of California, Berkeley, Tech. Rep. No. UCB/ERL M98/75, Dec. 1998. [17] C. C. Liu, “Design of a 100MHz 10bit analog to digital converter with pipeline architecture,” Master Thesis , Department of Electrical and Control Engineering, National Chiao Tung University, Taiwan, 2003. [18] M. Liu. (2004, May). Non-linearity impacts on switched-capacitor filter design. Extron Electronics. [Online] Available: http://www.commsdesign.com/article/ printableArticle.jhtml?articleID=21700450 [19] K. W. Moulding, J. R. Quartly, P. J. Rankin, R. S. Thompson, and G. A. Wilson, “Gyrator video filter IC with automatic tuning,” IEEE J. Solid-State Circuits, vol. 15, pp. 963-968, Dec. 1980. [20] K. Martin, and A. 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關鍵字(中)	切換式電容 頻疊失真 濾波器
關鍵字(英)	anti-aliasing switched-capacitor filter
口試委員	洪玉城 - 口試委員 陳春僥 - 口試委員 張順志 - 口試委員 黃俊岳 - 召集委員 劉濱達 - 指導教授
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國圖開放權限	暫不開放，開放日為： (No access until)：2010-07-16
繳交日期	2007-08-14

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